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DS2030Y/AB Single-Piece 256kb
Nonvolatile SRAM
Functional Diagram
CE
V CC
V TP REF
CURRENT-LIMITING
RESISTOR
DELAY TIMING
CIRCUITRY
CHARGER
UNINTERRUPTED
POWER SUPPLY
FOR THE SRAM
V CC
CE
RST
V SW REF
OE
WE
SRAM
DQ0 – 7
REDUNDANT LOGIC
ML
CURRENT-LIMITING
RESISTOR
REDUNDANT
SERIES FET
GND
OE
WE
A0 – A14
BATTERY-CHARGING/SHORTING
PROTECTION CIRCUITRY (UL RECOGNIZED)
DS2030
Detailed Description
The DS2030 is a 256kb (32kb x 8 bits) fully static, NV
memory similar in function and organization to the
DS1230 NV SRAM, but containing a rechargeable ML
battery. The DS2030 NV SRAM constantly monitors V CC
for an out-of-tolerance condition. When such a condition
occurs, the lithium energy source is automatically
switched on and write protection is unconditionally
enabled to prevent data corruption. There is no limit to
the number of write cycles that can be executed and no
additional support circuitry is required for microprocessor
interfacing. This device can be used in place of SRAM,
EEPROM, or flash components.
The DS2030 assembly consists of a low-power SRAM,
an ML battery, and an NV controller with a battery charg-
er, integrated on a standard 256-ball, 27mm 2 BGA sub-
strate. Unlike other surface-mount NV memory modules
that require the battery to be removable for soldering,
the internal ML battery can tolerate exposure to con-
vection reflow soldering temperatures allowing this sin-
gle-piece component to be handled with standard BGA
assembly techniques.
Two versions of the DS2030 are available that provide
either a 5% (DS2030AB) or 10% (DS2030Y) power-moni-
toring trip point. The DS2030 also contains a power-sup-
ply monitor output, RST , which can be used as a CPU
supervisor for a microprocessor.
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